The invention generally refers to a method of quasi-synchronously transferring clocking-, data-, and/or control signals between two or more data processing units and to a phase alignment means for enabling same.
FIGS. 1A-C show a block diagram and timing diagrams of how a synchronous and an asynchronous interface work. Since they are widely known, only the important summary points are dealt with in the following:
Synchronous Interface (FIG. 1A, B)
The clock signals of units A and B have the same frequency and the same phase relationship. PA1 One data transfer can occur every cycle via connecting cables 1 and/or 2. PA1 Any interface delays must be adjusted to exactly align the internal clocks of both units. For a system involving a cable and interface drivers, this may be a very difficult job to realize. PA1 The clock signals of units A and B have different frequencies and different phase relationships. PA1 Multiple cycles are required for every data transfer. PA1 Any interface delays can exist, within the required limits of propagation delay and skew. For this reason, many external interfaces from box to box are done asynchronously.
As can be seen from FIG. 1B, a synchronous interface can be used to send data from unit A to unit B or vice versa without waiting to see if unit B or A received each data transfer successfully (correctly). The synchronous interface, however, requires that the sender and receiver be in a "lock-step" with one another which means that the receiver reads the data at the same time the sender sends the data.
FIG. 1B shows an example, where a section of six clock cycles 1A . . . 6A, 1B . . . 6B respectively are used to transfer six data units (bits, bytes, words, etc. depending on the number of parallel lines) D1 . . . D6, D10 . . . D15 respectively from unit A to unit B and/or vice versa.
The clock pulses of the internal clock of unit A and unit B have the same frequency and phase, as can be seen from FIG. 1B. Data unit D1 which is sent during clock cycle 1A of unit's A internal clock via cable 1 will be received at unit B during the next clock cycle 2B of unit's B internal clock. Data unit D10 which is sent from unit B over cable 2 at the same time as data unit D1 will be received at unit A during clock cycle 2A of unit's A internal clock.
Asynchronous Interface (FIG. 1A, C)
Using an asynchronous interface, unit A sends data, one transfer at a time and waits to send the next transfer until unit B replies that it received the data correctly.
As can be seen from the pulse diagram in lines four and five of FIG. 1C, two more interface lines are necessary for transmitting control signals. In the case of a data transfer from unit A to unit B a control signal from unit A is sent to unit B, meaning new data is on the bus. The other control signal is a reply signal from unit B sent to unit A, meaning unit B read the data.
As further can be seen from lines three and eight of the pulse diagram in FIG. 1C, multiple cycles are required for every data transfer. To transfer a data unit D1 from unit A to unit B almost four clock A cycles are necessary until this data unit D1 is completely captured at unit B. When data from unit B have to be transferred asynchronously to unit A then the complete process has to be reversed.
As can be seen from the description above, both interfaces have their advantages and disadvantages. The advantage of a synchronous interface is, that one data transfer can occur every cycle. Its disadvantage, however, is that any interface delays must be adjusted to exactly align the internal clocks of both units. An asynchronous interface has the advantage, that any interface delays can exist, within the required limits of propagation delay and skew; its disadvantage, however, is that multiple cycles are required for any data transfer.
Therefore, it is the object of the present invention to avoid the disadvantages listed above of both interfaces and keep at the same time their advantages.